This page summarizes the common 8× B200 HGX/DGX node, one B200 GPU, and one physical Blackwell die. Values are separated into directly sourced specs and derived per-die estimates to avoid double-counting the dual-die package.
Most important correction: a B200 GPU is dual-die, but the CUDA-visible GPU has 148 SMs total, not 148 SMs per die.
Per die ≈ 74 active SMs is derived from 148 ÷ 2, not an independent CUDA device.
8 CUDA-visible B200 GPUs. NVIDIA DGX B200 lists 1,440 GB total GPU memory and 14.4 TB/s aggregate NVLink bandwidth.
One B200 package contains two physical Blackwell dies but is presented as one coherent GPU device.
Useful for architecture reasoning only. CUDA kernels see the whole B200 device, not an individual die.
| Precision / path | 8× B200 node | 1× B200 GPU | ≈1 die, derived | Meaning |
|---|---|---|---|---|
| FP4 Tensor Core | 72 dense / 144 sparse PFLOPS | 9 dense / 18 sparse PFLOPS | ≈4.5 dense / 9 sparse PFLOPS | AI inference-oriented low precision |
| FP8 / FP6 Tensor Core | 36 dense / 72 sparse PFLOPS | 4.5 dense / 9 sparse PFLOPS | ≈2.25 dense / 4.5 sparse PFLOPS | Training/inference Tensor Core formats |
| INT8 Tensor Core | 36 dense / 72 sparse POPS | 4.5 dense / 9 sparse POPS | ≈2.25 dense / 4.5 sparse POPS | Integer Tensor Core path |
| FP16 / BF16 Tensor Core | 18 dense / 36 sparse PFLOPS | 2.25 dense / 4.5 sparse PFLOPS | ≈1.125 dense / 2.25 sparse PFLOPS | Common DL training/inference path |
| TF32 Tensor Core | 8.8 dense / 17.6 sparse PFLOPS | 1.1 dense / 2.2 sparse PFLOPS | ≈0.55 dense / 1.1 sparse PFLOPS | Fast Tensor Core path for FP32 tensors |
| FP32 CUDA-core/SIMT | 600 TFLOPS | 75 TFLOPS | ≈37.5 TFLOPS | True FP32 path; not TF32 Tensor Core |
| FP64 / FP64 Tensor Core | 296 TFLOPS | 37 TFLOPS | ≈18.5 TFLOPS | HPC-oriented double precision path |
| Metric | 8× node | 1× GPU | ≈1 die |
|---|---|---|---|
| GPU memory | 1,440 GB total | 180 GB HBM3e* | ≈90 GB* |
| HBM bandwidth | 61.6 TB/s derived from per-GPU; NVIDIA pages also list ~62–64 TB/s | 7.7 TB/s | ≈3.85 TB/s |
| HBM stacks | 64 total, derived | 8 total | ≈4 |
| GPU-to-GPU NVLink | 14.4 TB/s aggregate | 1.8 TB/s per GPU | Not die-visible |
| Die-to-die link | Inside each GPU package | NV-HBI coherent single-device link | 10 TB/s chip-to-chip link |
*NVIDIA product datasheet for HGX B200 lists 180 GB HBM3e per GPU; the architecture paper describes a unified 192 GB HBM3e memory space. Treat 180 GB as the HGX/DGX product capacity exposed in current product specs.
| Metric | 1× B200 GPU | ≈1 die |
|---|---|---|
| Physical dies | 2 | 1 |
| Transistors | 208 billion | ≈104 billion |
| Active SMs | 148 total | ≈74 if evenly split |
| GPCs | 8 total | ≈4 if evenly split |
| L2 partitions | 4 total | ≈2 if evenly split |
| MIG | 7 instances supported | MIG applies at GPU level |
| TDP | Configurable up to 1,000 W for HGX B200 GPU | Not specified per die |
Use 148 SMs per B200 CUDA device. Do not multiply by two again for the two dies. If you have an 8-GPU node, the total active SM count is 8 × 148 = 1,184.
FP32 75 TFLOPS is the true FP32/SIMT product spec. TF32 1.1 / 2.2 PFLOPS is Tensor Core dense/sparse. A PyTorch float32 GEMM may use TF32 unless disabled.
| Value | Status | Reason |
|---|---|---|
| 8 B200 GPUs, 1,440 GB total memory, 14.4 TB/s NVLink aggregate | Direct NVIDIA DGX B200 spec | NVIDIA DGX B200 page and user guide list these node-level values. |
| 180 GB HBM3e, 7.7 TB/s, 75 TFLOPS FP32, 2.2 PFLOPS TF32 sparse, 18 PFLOPS FP4 sparse | Direct NVIDIA Blackwell/HGX B200 datasheet | These are listed under individual HGX B200 GPU specifications. |
| 2 dies, 208B transistors, 148 SMs, 8 GPCs, 8 HBM3e stacks, NV-HBI unified device | Direct from the B200 microbenchmarking paper | The paper explicitly describes one B200 GPU this way. |
| ≈74 SMs/die, ≈90 GB/die, ≈3.85 TB/s/die, ≈37.5 TFLOPS FP32/die | Derived | Calculated by dividing the GPU-level value by two. Useful for mental model, but not exposed as separate GPU devices. |