Intel EU/XVE Stall Counter Visualizer

Fast mental model · audited

ALUWR / SBID

Both are dependency-side waits, but different dependencies: ALUWR is waiting for an ALU write/result; SBID is scoreboard token/dependency state. Neither alone proves DRAM latency or physical write-port contention.

PIPESTALL

The instruction can be ready yet unable to enter the target pipe. Intel VTune gives a GRF bank conflict as a concrete example.

SENDWR

This one must be source-scoped: Arc/ACM = waiting for SEND to write GRF; Lunar Lake-style metric = waiting for SEND dispatch from XVE.

Compact audited reference

Counter	Documented core meaning	Source scope	Good tiny mental model
EU_STALL_ALUWR	Waiting for ALU to write GRF/ACC	Arc/ACM PRM	producer → destination not written → dependent consumer waits
EU_STALL_SENDWR	Arc: SEND writes GRF; newer Xe: SEND dispatch wait	Generation-sensitive	do not use one universal flow
EU_STALL_SBID	Scoreboard token/dependency unavailable	Arc/ACM + VTune + LNL	async tracked work holds scoreboard state → later work waits
EU_STALL_PIPESTALL	Ready instruction cannot dispatch to target pipe	VTune XVE / LNL	won arbitration → GRF/resource conflict → pipe cannot accept
EU_STALL_PS_DEPENDENCY	Pixel Shader dependency	Lunar Lake metric	graphics dependency remains unresolved
EU_STALL_INSTFETCH	Waiting for Instruction Fetch	Arc/ACM + VTune	new PC → target instruction not available
EU_STALL_CONTROL	Waiting for Branch unit / branch completion	VTune XVE / LNL	conditional branch → control unit unavailable
EU_STALL_BARRIER	Waiting for synchronization dependency; Arc mentions Gateway Notify	Arc/ACM + VTune	some work-items arrive → others late → barrier wait
EU_STALL_OTHER	Other dependency; Flag/EoT are explicit examples	Arc/ACM + LNL	flag/predicate dependency not covered elsewhere

Audit sources

Primary: Intel Arc A-Series / ACM PRM Vol. 13 event definitions; Intel VTune — Reasons for XVE Stalls; Intel VTune — XVE Pipe Stall; Intel VTune — XVE SBID Stall.
Cross-check for newer Xe/Lunar Lake metric wording: Mesa Intel performance-metric XML (including PS_DEPENDENCY and newer SENDWR wording).